JTAG/Boundary Scan Test

• Cost efficient JTAG-Tool
  For interactive board level debugging and production tests
• IO-Filtering
  Observe IOs of interest only
• Pin-File parsing
  Use your HDL top-level pin names to find signals quickly
• Scripting interface
  For production tests and all repetitive tasks

Have you ever attempted to measure signals between two ball grid arrays and then noticed that you forgot to insert test pads? Has the price of JTAG tools kept you from using Boundary Scan Tests?

With Hpe®_JTAG Gleichmann Electronics Research introduces a cost efficient JTAG tool allowing you to debug and test your PCBs and ICs. Hpe®_JTAG gives the design engineer full control over the logical states of any I/O-pin or register that is accessible via Boundary Scan at a fraction of the cost of high-end JTAG tools. Opposed to most low-cost JTAG tools, Hpe®_JTAG is fully scriptable, hence tests can be automated for production.

IO-Filtering
Observe IOs of interest only

&

Pin-File parsing
Use your HDL top-level pin
names to find signals quickly

Hpe®_JTAG^_AE

Hpe®_JTAG^AE will only allow Actel devices in the JTAG-chain. If a non-Actel device is in the JTAG-chain the user has to upgrade to the Hpe®_JTAG.

Short description:

Hpe®_JTAG^AE is a tool for interactive PCB debugging.
Hpe®_JTAG^AE allows users to load pin names BSDL files and/or from pin files generated during FPGA synthesis (*.rpt files).
A powerful Python scripting interface allows users to automate repetitive tasks and/or add functionality to the tool (for example to read out A/D register values for Actel Fusion FPGAs).

Demo version (Hpe®_JTAG^AE Demo):

Requires a license file that will be generated free of charge for MSC customers only. The demo version will include:

• A simulator (no real hardware required)
• Support for Actel IGLOO AGL125V5

Download the current demo version

Request more information and your demo license at act-licensing@msc-ge.com